Abstract

Digital systems consist of thousands of digital circuit blocks operating in the background, working in their simplest form such as addition, subtraction, multiplication, division. In exponential expressions like square roots and cube roots, just like these circuits, it is found in many digital systems and performs tasks. Although these processes seem to be used only in circuits carrying out mathematical operations, they actually take an active role in solving many engineering problems. In this study, a digital circuit design that computes both the integer and a floating point exponent of a 32-bit floating-point number has been realized. This digital circuit, which is coded with VHDL language, can be used from beginner to advanced level in FPGA based systems. This digital circuit, which is coded with VHDL language, can be used from beginner to advanced level in FPGA based systems. In addition, three floating IP cores - logarithm, multiplication and exponent - were used in this digital circuit, and results were obtained with a total of five finite state machines in sixty-six clock pulse time.

References

[1] Kösten MM, Efe MÖ. Implementation of Discrete Time Sliding Mode Control with Floating Point Arithmetic on an FPGA. Otomatik Kontrol Ulusal Toplantısı 2015.

[2] Koyuncu İ, Çetin Ö, Katırcıoğlu F, Tuna M. Edge dedection application with FPGA based Sobel operator. 23nd IEEE Signal Processing and Communications Applications Conference (SIU) 2015; 1829-1832.

[3] Çavuşlu MA, Karakuzu C, Şahin S, Karakaya F. Yapay sinir ağı eğitiminin IEEE 754 kayan noktalı sayı formatı ile FPGA tabanlı gerçeklenmesi. İstanbul: İstanbul Teknik Üniversitesi (GOMSİS) 2008.

[4] Kamm L, Willemson J. Secure floating point arithmetic and private satellite collision analysis. Int. J. Inf. Secur. 2015; 14:531-548.

[5] Higham NJ, Pranesh S. Simulating low precision floating-point arithmetic. SIAM Journal on Scientific Computing 2019; 41:585-602.

[6] Brain M, Tinelli C, Rümmer P, Wahl T. An automatable formal semantics for IEEE-754 floating-point arithmetic. IEEE 22nd Symposium on Computer Arithmetic 2015; 160-167.

[7] Catrina O. Round-efficient protocols for secure multiparty fixed-point arithmetic. International Conference on Communications (COMM) 2018; 431-436.

[8] Nane R, Sima VM, Pilato C, Choi J, Fort B, Canis A, Anderson J.  A survey and evaluation of FPGA high-level synthesis tools. EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2015; 35:1591-1604.

[9] Zhang C, Prasanna V. Frequency domain acceleration of convolutional neural networks on CPU-FPGA shared memory system. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2017.

[10] Tolba MF, Fouda ME, Hezayyin HG, Madian AH, Radwan AG.  Memristor FPGA IP core implementation for analog and digital applications. IEEE Transactions on Circuits and Systems II: Express Briefs 2018; 66:1381-1385.

[11] Kachhwal P, Rout BC. Novel Square Root Algorithm and its FPGA Implementation. International Conference on Signal Propagation and Computer Technology (ICSPCT) 2014:158-162.

[12] Zhou Z, Hu J. A Novel Square Root Algorithm and its FPGA Simulation. Journal of Physics: Conference Series 2019.

[13] Guardia CM, Boemo E. FPGA implementation of a binary32 floating point cube root. IEEE Southern Conference on Programmable Logic (SPL) 2014.

[14] Wang T, Wang C, Zhou X, Chen H. A Survey of FPGA Based Deep Learning Accelerators: Challenges and Opportunities. Distributed, Parallel, and Cluster Computing 2018:1-10.

[15] Malík P. High throughput floating point exponential function implemented in FPGA. IEEE Computer Society Annual Symposium on VLSI 2015:97-100.

[16] Rao YS, Kamaraju M, Ramanjaneyulu DVS. An FPGA implementation of high speed and area efficient double-precision floating point multiplier using Urdhva Tiryagbhyam technique. IEEE Conference on Power, Control, Communication and Computational Technologies for Sustainable Growth (PCCCTSG) 2015.

[17] Perera DG. Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications. 12th FPGA world Conference 2015:15-20.

[18] Tolba MF, AbdelAty AM, Soliman NS, Said LA, Madian AH, Azar AT, Radwan AG. FPGA implementation of two fractional order chaotic systems. AEU-International Journal of Electronics and Communications 2017; 78:162-172.

[19] Abdelkrim H, Othman SB, Saoud SB. Reconfigurable SoC FPGA based: Overview and trends. IEEE International Conference on Advanced Systems and Electric Technologies (IC_ASET) 2017.

[20] Dereli S. FPGA ile Gömülü Sistemler ve Sayısal Devre Tasarımı. 1st ed. Ankara: NOBEL Akademik Yayıncılık; 2020.

[21] Dereli S. Yüksek Hızlı FPGA ile Yeni Bir LFSR Tabanlı 32-Bit Kayan Noktalı Rastgele Sayı Üreteci Tasarımı. International Journal of Advances in Engineering and Pure Sciences 2020; 32:219-228.

[22] Bilsby DCM, Walke RL, Smith RWM. Comparison of a programmable DSP and a FPGA for real-time multiscale convolution. IEE Colloquium on High Performance Architectures for Real-Time Image Processing, 1998.

[23] Chase J, Nelson B, Bodily J, Wei Z, Lee DJ. Real-time optical flow calculations on FPGA and GPU architectures: a comparison study. 16th IEEE International Symposium on Field-Programmable Custom Computing Machines 2008:173-182.

[24] Allaire FC, Tarbouchi M, Labonté G, Fusina G. FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning. Journal of Intelligent and Robotic Systems 2008; 54:495–510.

[25] Muslim FB, Ma L, Roozmeh M, Lavagno L. Efficient FPGA implementation of OpenCL high-performance computing applications via high-level synthesis. IEEE Access 2017; 5:2747-2762.

[26] Torun MU, Yilmaz O, Akansu AN. FPGA, GPU, and CPU implementations of Jacobi algorithm for eigenanalysis. Journal of Parallel and Distributed Computing 2016; 96:172-180.

[27] Rizvi STH, Cabodi G, Patti D, Gulzar MM. Comparison of GPGPU based robotic manipulator with other embedded controllers. 2016 International Conference on Development and Application Systems (DAS) 2016:10-15.

[28] Gizopoulos D, Papadimitriou G, Chatzidimitriou A, Reddi VJ, Salami B, Unsal OS, Leng J. Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies. IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS) 2019:129-134.

[29] Lee H, Kim K, Kwon Y, Hong E. Real-time particle swarm optimization on FPGA for the optimal message-chain structure. Electronics 2018;7:274.